View ALD1722_337377.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ADVANCED LINEAR DEVICES, INC.
ALD1722E/ALD1722 EPADTM OPERATIONAL AMPLIFIER
KEY FEATURES * * * * * * * * * * EPAD ( Electrically Programmable Analog Device) User programmable VOS trimmer Computer-assisted trimming Rail-to-rail input/output Compatible with standard EPAD Programmer High precision through in-situ circuit precision trimming Reduce or eliminate VOS, PSRR, CMRR and TCVOS errors System level "calibration" capability In-System Programming capable Electrically programmable to compensate for external component tolerances * Achieve 0.01pA input bias current and 25V input offset voltage simultaneously * Compatible with industry standard pinout GENERAL DESCRIPTION The ALD1722E/ALD1722 is a monolithic rail-to-rail precision CMOS operational amplifier with integrated user programmable EPAD (Electrically Programmable Analog Device) based offset voltage adjustment. The ALD1722E/ALD1722 is a direct replacement of the ALD1702 operational amplifier, with the added feature of user-programmable offset voltage trimming resulting in significantly enhanced total system performance and user flexibility. EPAD technology is an exclusive ALD design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. It utilizes CMOS FETs as in-circuit elements for trimming of offset voltage bias characteristics with the aid of a personal computer under software control. Once programmed, the set parameters are stored indefinitely within the device even after power-down. EPAD offers the circuit designer a convenient and costeffective trimming solution for achieving the very highest amplifier/system performance. The ALD1722E/ALD1722 operational amplifier features rail-to-rail input and output voltage ranges, tolerance to over-voltage input spikes of 300mV beyond supply rails, high capacitive loading up to 4000pF, extremely low input currents of 0.01pA typical, high open loop voltage gain, useful bandwidth of 1.5 MHz, slew rate of 2.1 V/s, and low supply current of 0.8mA.
BENEFITS * Eliminates manual and elaborate system trimming procedures * Remote controlled automated trimming * In-System Programming capability * No external components * No internal chopper clocking noise * No chopper dynamic power dissipation * Simple and cost effective * Small package size * Extremely small total functional volume size * Low system implementation cost * Low power
APPLICATIONS * * * * * * * * * * * * * * Sensor interface circuits Transducer biasing circuits Capacitive and charge integration circuits Biochemical probe interface Signal conditioning Portable instruments High source impedance electrode amplifiers Precision Sample and Hold amplifiers Precision current to voltage converter Error correction circuits Sensor compensation circuits Precision gain amplifiers Periodic In-system calibration System output level shifter
PIN CONFIGURATION
VE1
1 2 3 4 TOP VIEW DA, PA, SA PACKAGE 2
8 7 6 5
VE2 V+ OUT N/C
ORDERING INFORMATION
Operating Temperature Range* -55C to +125C 0C to +70C 0C to +70C
8-Pin CERDIP Package 8-Pin Small Outline Package (SOIC) 8-Pin Plastic Dip Package
-IN +IN V-
ALD1722E DA ALD1722 DA
ALD1722E SA ALD1722 SA
ALD1722E PA ALD1722 PA
* Contact factory for industrial temperature range
ALD1722E/ALD1722
Advanced Linear Devices
1
FUNCTIONAL DESCRIPTION The ALD1722E/ALD1722 uses EPADs as in-circuit elements for trimming of offset voltage bias characteristics. Each ALD1722E/ALD1722 has a pair of EPAD-based circuits connected such that one circuit is used to adjust VOS in one direction and the other is used to adjust VOS in the other direction. Functional Description of ALD1722E While each of the EPAD devices is a monotonically adjustable programmable device, the VOS of the ALD1722E can be adjusted many times in both directions. Once programmed, the set VOS levels are stored permanently, even when the device power is removed. The ALD1722E provides the user with an operational amplifier that can be trimmed with user application-specific programming or in-system programming conditions. User application-specific circuit programming refers to the situation where the Total Input Offset Voltage of the ALD1722E can be trimmed with the actual intended operating conditions. The ALD1722E is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. It also has a guaranteed offset voltage program range, which is ideal for applications that require electrical offset voltage programming. For example, an application circuit may have +6V and -2.5V power supplies, and the operational amplifier input is biased at +0.7V, and the average operating temperature is at 55C. The circuit can be wired up to these conditions within an environmental chamber, and the ALD1722E can be inserted into a test socket connected to this circuit while it is being electrically trimmed. Any error in VOS due to these bias conditions can be automatically zeroed out. The Total VOS error is now limited only by the adjustable range and the stability of VOS, and the input noise voltage of the operational amplifier. Therefore, this Total VOS error now includes VOS as V OS is traditionally specified; plus the V OS error contributions from PSRR, CMRR, TCVOS, and noise. Typically this total VOS error term (VOST) is approximately 25V for the ALD1722E. The VOS contribution due to PSRR, CMRR, TCVOS and external components can be large for operational amplifiers without trimming. Therefore the ALD1722E with EPAD trimming is able to provide much improved system performance by reducing these other sources of error to provide significantly reduced VOST. In-System Programming refers to the condition where the EPAD adjustment is made after the ALD1722E has been inserted into a circuit board. In this case, the circuit design must provide for the ALD1722E to operate in normal mode and in programming mode. One of the benefits of in-system programming is that not only is the ALD1722E offset voltage from operating bias conditions accounted for, any residual errors introduced by other circuit components, such as resistor or sensor induced voltage errors, can also be corrected. In this way, the "in-system" circuit output can be adjusted to a desired level eliminating other trimming components.
Functional Description of ALD1722 The ALD1722 is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset voltage. The ALD1722 offers similar programmable features as the ALD1722E, but with more limited offset voltage program range. It is intended for standard operational amplifier applications where little or no electrical programming by the user is necessary. USER PROGRAMMABLE Vos FEATURE Each ALD1722E/ALD1722 has two pins named VE1 and VE2 which are internally connected to an internal offset bias circuit. VE1/VE2 have initial typical values of 1.6 Volt. The voltage on these pins can be programmed using the ALD E100 EPAD Programmer and the appropriate Adapter Module. The useful programming range of VE1 and VE2 is 1.6 Volt to 3.5 Volts. VE1 and VE2 pins are programming pins, used during programming mode. The Programming pin is used during electrical programming to inject charge into the internal EPADs. Increases of VE1 decrease the offset voltage while increases of VE2 increase the offset voltage of the operational amplifier. The injected charge is permanently stored and determines the offset voltage of the operational amplifier. After programming, VE1 and VE2 terminals must be left open to settle on a voltage determined by internal bias currents. During programming, the voltages on VE1 or VE2 are increased incrementally to set the offset voltage of the operational amplifier to the desired VOS. Note that desired VOS can be any value within the offset voltage programmable ranges, and can be either zero, a positive value or a negative value. This VOS value can also be reprogrammed to a different value at a later time, provided that the useful VE1 or VE2 programming voltage range has not been exceeded. VE1 or VE2 pins can also serve as capacitively coupled input pins. Internally, VE1 and VE2 are programmed and connected differentially. Temperature drift effects between the two internal offset bias circuits cancel each other and introduce less net temperature drift coefficient change than offset voltage trimming techniques such as offset adjustment with an external trimmer potentiometer. While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by the EPAD Programmer. In-system programming requires the ALD1722E/ALD1722 application circuit to accommodate these programming pulses. This can be accomplished by adding resistors at certain appropriate circuit nodes. For more information, see Application Note AN1700.
2
Advanced Linear Devices
ALD1722E/ALD1722
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+ Differential input voltage range Power dissipation Operating temperature range PA,SA package DA package Storage temperature range Lead temperature, 10 seconds 13.2V -0.3V to V+ +0.3V 600 mW 0C to +70C -55C to +125C -65C to +150C +260C
OPERATING ELECTRICAL CHARACTERISTICS TA = 25oC VS = 2.5V unless otherwise specified
Parameter Supply Voltage
Symbol
VS V+ VOS i
2
Min
2.0 4.0
1722E Typ
Max
5.0 10.0
Min
2.0 4.0
1722 Typ
Max
5.0 10.0
Unit
V V V mV
Test Conditions
Single Supply RS 100K
Initial Input Offset Voltage 1 Offset Voltage Program Range Programmed Input Offset 3 Voltage Error Total Input Offset Voltage
4
25 5 8 25
50 0.5 50
40 3 40
90
VOS VOS
90
V
At user specified target offset voltage At user specified target offset voltage TA = 25C 0C TA +70C TA = 25C 0C TA +70C V+ = +5V; notes 2,5 VS = 2.5V
VOST
25
50
40
90
V
Input Offset Current 5
IOS
0.01
10 280 10 280
0.01
10 280 10 280
pA pA pA pA V V V/C dB
Input Bias Current 5
IB
0.01
0.01
Input Voltage Range
6
VIR
-0.3 -2.8 1014 5 85
5.3 +2.8
-0.3 -2.8 1014 7 85
5.3 +2.8
Input Resistance Input Offset Voltage Drift 7 Initial Power Supply Rejection Ratio 8 Initial Common Mode Rejection Ratio
8
RIN TCVOS PSRR i
RS 100K RS 100K
CMRR i
97
97
dB
RS 100K
Large Signal Voltage Gain
AV
50
250 500 0.002 4.998 -2.44 2.44 8 0.01
50
250 500 0.002 4.998 -2.44 2.44 8 0.01 -2.35
V/mV V/mV V V V V mA
RL =10K RL 1M R L =1M V+ = 5V 0C TA +70C R L =10K 0C TA +70C
Output Voltage Range
VO low VO high VO low VO high ISC
4.99 2.35
4.99 -2.35 2.35
Output Short Circuit Current
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
ALD1722E/ALD1722
Advanced Linear Devices
3
OPERATING ELECTRICAL CHARACTERISTICS (cont'd) TA = 25oC VS = 2.5V unless otherwise specified
1722E
Parameter Supply Current Symbol IS Min Typ 0.8 Max 1.5 Min
1722
Typ 0.8 Max 1.5 Unit mA Test Conditions VIN = 0V No Load VS = 2.5V
Power Dissipation Input Capacitance Maximum Load Capacitance
PD CIN CL
4.0 1 400 4000 26 0.6 1.0 1.4 1.5 2.1
7.5
4.0 1 400 4000 26 0.6 1.0 1.4 1.5 2.1
7.5
mW pF pF pF nV/ Hz fA/ Hz MHz V/s
Gain = 1 Gain = 5 f = 1KHz f =10Hz
Input Noise Voltage Input Current Noise Bandwidth Slew Rate
en in BW SR
AV = +1 RL = 10K RL = 10K RL = 10K, CL = 100pF 0.01% 0.1% AV = -1, RL= 5K CL = 50pF
Rise time Overshoot Factor
tr
0.2 10
0.2 10
s %
Settling Time
ts
8.0 3.0
8.0 3.0
s s
T A = 25 oC V S = 2.5V unless otherwise specified
1722E
Parameter Average Long Term Input Offset Voltage Stability 9 Initial VE Voltage Symbol VOS time VE1 i VE2 i VE1 VE2 i eb 1.5 Min Typ 0.02 Max Min
1722
Typ 0.02 Max Unit V/ 1000 hrs V Test Conditions
1.6
2.6
Programmable VE Range
2.0
0.5
V
VE Pin Leakage Current
-5
-5
A
4
Advanced Linear Devices
ALD1722E/ALD1722
V S = 2.5V -55C TA +125C unless otherwise specified
1722E
Parameter Initial Input Offset Voltage Input Offset Current Input Bias Current Initial Power Supply Rejection Ratio
8
1722
Max Min Typ 0.7 2.0 2.0 2.0 2.0 85 Max Unit mV nA nA dB RS 100K Test Conditions RS 100K
Symbol VOS i IOS IB PSRR i
Min
Typ 0.5
85
Initial Common Mode 8 RejectionRatio Large Signal Voltage Gain Output Voltage Range
CMRR i
97
97
dB
RS 100K
AV VO low VO high
10
25 -2.4 2.4 -2.3
10
25 -2.4 2.4 -2.3
V/mV V V
RL 10K RL 10K
2.3
2.3
TA = 25 oC V S = 5.0V unless otherwise specified
1722E
Parameter Initial Power Supply Rejection Ratio 8 Initial Common Mode 8 Rejection Ratio Large Signal Voltage Gain Output Voltage Range Symbol PSRR i Min Typ 85 Max Min
1722
Typ 85 Max Unit dB Test Conditions RS 100K
CMRRi
97
97
dB
RS 100K
AV VO low VO high BW SR
250 -4.90 4.93 1.7 2.8 -4.80 4.80
250 -4.90 4.93 1.7 2.8 -4.80
V/mV V
RL = 10K R L = 10K
4.80
Bandwidth Slew Rate
MHz V/s AV = +1, CL = 50pF
ALD1722E/ALD1722
Advanced Linear Devices
5
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE
7
OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE AND TEMPERATURE
1000
COMMON MODE INPUT VOLTAGE RANGE (V)
5 4 3 2 1 0 0 1 2 3 4 5 6 7
OPEN LOOP VOLTAGE GAIN (V/mV)
6
TA = 25C
} -55C } +25C
100
} +125C
10 RL= 10K RL= 5K 1 0 2 4 SUPPLY VOLTAGE (V) 6 8
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION OF AMBIENT TEMPERATURE
1000
SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE
2.5 INPUTS GROUNDED OUTPUT UNLOADED TA = -55C -25C 1.0 0.5 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V) +25C +80C +125C
INPUT BIAS CURRENT (pA)
100 10
SUPPLY CURRENT (mA)
VS = 2.5V
2.0 1.5
1.0
0.1 0.01 -50 -25 0 25 50 75 100 125 AMBIENT TEMPERATURE (C)
CHANGE IN INPUT OFFSET VOLTAGE AS A FUNCTION OF CHANGE IN VE1 AND VE2
CHANGE IN INPUT OFFSET VOLTAGE VOS (mV)
5 4
120 100 80 60 40 20 0 -20
OPEN LOOP VOLTAGE AS A FUNCTION OF FREQUENCY
OPEN LOOP VOLTAGE GAIN (dB)
3 2 1 0 -1 -2 -3 -4 -5 0.0 0.5 1.0 1.5 2.0
VE2
PHASE SHIFT IN DEGREES
VS = 2.5V TA = 25C 0 45 90 135 180 1 10 100 1K 10K 100K 1M 10M
VE1
2.5
3.0
CHANGE IN VE1 AND VE2 (V)
FREQUENCY (Hz)
6
Advanced Linear Devices
ALD1722E/ALD1722
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE SWING AS A FUNCTION OF SUPPLY VOLTAGE
25C TA 125C
RL = 10K
7
LARGE - SIGNAL TRANSIENT RESPONSE
5V/div VS = 2.5V TA = 25C RL = 10K CL = 50pF
OUTPUT VOLTAGE SWING (V)
6 5 4 3 2 0
RL = 10K RL = 2K
1V/div
1 2 3 4 5 6 7
2s/div
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF LOAD RESISTANCE
1000
SMALL - SIGNAL TRANSIENT RESPONSE
100mV/div VS = 2.5V TA = 25C RL = 10K CL = 50pF
OPEN LOOP VOLTAGE GAIN (V/mV)
100 VS = 2.5V TA = 25C
10
20mV/div 1 1K 10K 100K 1000K
2s/div
LOAD RESISTANCE ()
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE BEFORE AND AFTER EPAD PROGRAMMING
100 EXAMPLE B: VOST AFTER EPAD PROGRAMMING VOST TARGET = -750V EXAMPLE A: VOST AFTER EPAD PROGRAMMING VOST TARGET = 0.0V
PERCENTAGE OF UNITS (%)
80
60 VOST BEFORE EPAD PROGRAMMING
40
20
0 -2500 -2000 -1500 -1000 -500 0 500 1000 1500 2000 2500
TOTAL INPUT OFFSET VOLTAGE (V)
ALD1722E/ALD1722
Advanced Linear Devices
7
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE (V)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500 PSRR = 80 dB 400 EXAMPLE A: VOS EPAD PROGRAMMED AT VSUPPLY = +5V EXAMPLE B: VOS EPAD PROGRAMMED AT VSUPPLY = +8V
300
200
100
0 0 1 2 3 4 5 6 7 8 9 10
SUPPLY VOLTAGE (V)
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500 VSUPPLY = 5V CMRR = 80dB 400
300
200
EXAMPLE B: VOS EPAD PROGRAMMED AT VIN = -4.3V
EXAMPLE A: VOS EPAD PROGRAMMED AT VIN = 0V
100
0 -5 -4 -3 -2 -1 0
EXAMPLE C: VOS EPAD PROGRAMMED AT VIN = +5V 1 2 3 4 5
COMMON MODE VOLTAGE (V)
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO CHANGE IN COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50 COMMON MODE VOLTAGE RANGE OF 0.5V 40
30 VOS EPAD PROGRAMMED AT COMMON MODE VOLTAGE OF 0.25V
20 CMRR = 80dB 10
0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
COMMON MODE VOLTAGE (V)
8
Advanced Linear Devices
ALD1722E/ALD1722
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various contributing sources is minimized under different sets of user-specified operating conditions
2500
2500
TOTAL INPUT OFFSET VOLTAGE (V)
TOTAL INPUT OFFSET VOLTAGE (V)
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE A VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE B VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
+
X
+
X
2500
TOTAL INPUT OFFSET VOLTAGE (V)
2500
TOTAL INPUT OFFSET VOLTAGE (V)
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE C VOS BUDGET AFTER EPAD PROGRAMMING VOS BUDGET BEFORE EPAD PROGRAMMING
2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 EXAMPLE D VOS BUDGET BEFORE EPAD PROGRAMMING VOS BUDGET AFTER EPAD PROGRAMMING
+
X
+
X
Device input VOS PSRR equivalent VOS
Total Input VOS after EPAD Programming
+
X
CMRR equivalent VOS TA equivalent VOS Noise equivalent VOS External Error equivalent VOS
ALD1722E/ALD1722
Advanced Linear Devices
9
DEFINITIONS AND DESIGN NOTES:
1. Initial Input Offset Voltage is the offset voltage of the ALD1722E/ALD1722 operational amplifier as shipped from the factory. The device has been pre-programmed and tested for programmability. 2. Offset Voltage Program Range is the range of adjustment of user specified target offset voltage. This is typically an adjustment in either the positive or the negative direction of the input offset voltage from an initial offset voltage. The input offset program pins, VE1 or VE2, change the input offset voltage in the negative or positive direction, respectively. User specified target offset voltage can be any offset voltage within this programming range. 3. Programmed Input Offset Voltage Error is the final offset voltage error after programming, when the Input Offset Voltage is at target Offset Voltage. This parameter is sample tested. 4. Total Input Offset Voltage is the same as Programmed Input Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also includes offset voltage contributions from input offset voltage, PSRR, CMRR, TCVos and noise. It can also include errors introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is not necessarily zero offset voltage, but an offset voltage set to compensate for other system errors as well. This parameter is sample tested. 5. The Input Offset and Bias Currents are essentially input protection diode reverse bias leakage currents. This low input bias current assures that the analog signal from the source will not be distorted by it. For applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage having a separate input offset voltage. While Total Input Offset Voltage can be trimmed to a desired target value, it is essential to note that this trimming occurs at only one selected input bias voltage. Depending on the selected input bias voltage relative to the power supply voltages, offset voltage trimming may affect one or both input stages. For the ALD1722E/ALD1722, the switching point between the two stages occur at approximately 1.5V above the negative supply voltage 7. Input Offset Voltage Drift is the average change in Total Input Offset Voltage as a function of ambient temperature. This parameter is sample tested. 8. Initial PSRR and initial CMRR specifications are provided as reference information. After programming, error contribution to the offset voltage from PSRR and CMRR is set to zero under the specific power supply and common mode conditions, and becomes part of the Programmed Input Offset Voltage Error. 9. Average Long Term Input Offset Voltage Stability is based on input offset voltage shift through operating life test at 125 degrees C extrapolated to Ta = 25 degrees C, assuming activation energy of 1.0eV. This parameter is sample tested.
ADDITIONAL DESIGN NOTES:
A. The ALD1722E/ALD1722 is internally compensated for unity gain stability using a novel scheme which produces a single pole role off in the gain characteristics while providing more than 70 degrees of phase margin at unity gain frequency. A unity gain buffer using the ALD1722E/ALD1722 will typically drive 400pF of external load capacitance; in the inverting unity gain configuration, it can drive up to 800pF of load capacitance. B. The ALD1722E/ALD1722 has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail to rail input common mode voltage range. The switching point between the two differential stages is 1.5V above negative supply voltage. For applications such as inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5V operation), the common mode voltage does not make excursions below this switching point. However, this switching does take place if the operational amplifier is connected as a railto- rail unity gain buffer and the design must allow for input offset voltage variations. C. The output stage consists of class AB complementary output drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD1722E/ALD1722 an effective analog signal buffer for high source impedance sensors, transducers, and other circuit networks. D. The ALD1722E/ALD1722 has static discharge protection. However, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. The user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages to not exceed 0.3V of the power supply voltage levels. E. VE1 and VE2 are high impedance terminals, as the internal bias currents are set very low to a few microamperes to conserve power. For some applications, these terminals may need to be shielded from external coupling sources. For example, digital signals running nearby may cause unwanted offset voltage fluctuations. Care during the printed circuit board layout to place ground traces around these pins and to isolate them from digital lines would generally eliminate such coupling effects. In addition, optional decoupling capacitors of 1000pF or greater value can be added to VE1 and VE2 terminals. F. The ALD1722E/ALD1722 is designed for use in low voltage, micro-power circuits. The maximum operating voltage during normal operation should remain below 10 Volts at all times. Care should be taken to insure that the application in which the devices are used would not experience any positive or negative transient voltages that cause any of the terminal voltages to exceed this limit. G. All inputs or unused pins except VE1 and VE2 pins should be connected to a supply voltage such as Ground so that they do not become floating pins, since input impedance at these pins is very high. If any of these pins are left undefined, they may cause unwanted oscillation or intermittent excessive current drain. As these devices are built with CMOS technology, normal operating and storage temperature limits, ESD and latchup handling precautions pertaining to CMOS device handling should be observed.
10
Advanced Linear Devices
ALD1722E/ALD1722

▲Up To Search▲

Price & Availability of ALD1722

	To Download ALD1722 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .